1. Trainer, Introduction of Basic Verilog and FPGA Design, 9-12 January 2017, Faculty of Biosciences and Medical Engineering, Universiti Teknologi Malaysia.
2. Instructor of UTM-UTHM RACE Program, HW/SW Co-design on Nios II-based Embedded System – Part I, 1-2 June 2014, Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia.
3. Invited Trainer by Dream Catcher Consulting Sdn. Bhd, Quick Start to Altera FPGA Implementation Platform – Part II, 28 February & 1 March 2014, Faculty of Biosciences and Medical Engineering, Universiti Teknologi Malaysia.
4. Invited Trainer by Dream Catcher Consulting Sdn. Bhd, Quick Start to Altera FPGA Implementation Platform – Part I, 29-30 November & 1 December 2013, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
5. Participant, Safety and Health at Work organized by Board of Engineers Malaysia (BEM), 14-15 May 2013, Universiti Teknologi Malaysia.
6. Participant, Engineering Management Practice organized by Board of Engineers Malaysia (BEM), 22-23 April 2013, Universiti Teknologi Malaysia.
7. Participant, Peer Instruction Workshop, 28-30 March 2013, Universiti Teknologi Malaysia.
8. Participant, Workshop on Writing to High Impact Journal, 12-14 March 2013, Universiti Teknologi Malaysia.
9. Participant, Kursus Induksi Siri 2/2012 (Kumpulan Pengurusan & Professional), 26 November – 9 December 2012, Universiti Teknologi Malaysia.
10. Participant, Short Course on Open Source Hospital Info Systems Development, 23-24 October 2012, United Nations University, International Institute for Global Health (UNU-IIGH), UKM Medical Center, Cheras, Malaysia.
11. Participant, Bengkel Penilaian Outcome Based Education (OBE) UTMSpace, 19-21 October 2012, Melaka, Malaysia, organized by UTMSpace, Universiti Teknologi Malaysia.
12. Participant, UTM Peer Instruction Online Training, 17 October 2012, Universiti Teknologi Malaysia.
13. Participant, Kolokium Kursus Matematik dan Kursus-Kursus Kejuruteraan Berteraskan Matematik, 26 September 2012, Universiti Teknologi Malaysia.
14. Participant, Tapping the power of the Virtual in building the future for WorldClass Healthcare System, 11 September 2012, School of Engineering, Temasek Polytechnic, Singapore, organized by SingHealth, Temasek Polytechnic and Advent2 Labs.
15. Participant, Kursus Penasihatan Akademik untuk Penasihat Akademik (PA) Tahun 1 Sesi 2012/2013, 29-30 August 2012, Universiti Teknologi Malaysia.
16. Participant, Short Course on FPGA-based Implementation of Signal Processing Systems, 25-26 June 2012, The Royale Bintang Kuala Lumpur, Malaysia, organized by Tekbac.
17. Participant, Kursus OBE – Assessment & CQI, 5-6 June 2012, Universiti Teknologi Malaysia.
18. Guest Lecturer, Design Optimization Technique of Digital Circuit Design at Register Transfer Level, 14th March 2011, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
19. Invited Speaker, Electronic System Level Modelling using SystemC, 24th March – 9th June 2010, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
20. Guest Lecturer, Introduction of Verilog Design Testbench, 16th March 2010, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
21. Teaching Assistant, MEL 1173 – Advanced Digital System Design (Post Graduate subject), 2009/2010-Sem II, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
22. Lab Facilitator, SEW 4722 – ECAD Problem Based Laboratory, HW/SW Co-design of a Nios II-based Embedded System, 2009/2010-Sem I, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
23. Participant, MSC Malaysia Industry Academia Collaboration: MDeC-Altera Train-the-Trainer: Digital System Design on FPGA Platform, 15th – 19th December 2008, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by Multimedia Development Corporation (MDeC).
24. Instructor, VLSI Digital System Design, 3rd – 29th December 2007, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by MDeC’s Undergraduate Skills Programme (USP).
25. Participant, Design and Test of System-on-Chip Integrated Circuits, 16th August 2007, Universiti Putra Malaysia, organized by Institute of Electrical & Electronic Engineers Circuits & Systems Society Malaysia Chapter.
26. Instructor, VLSI Digital System Design, 14th May – 9th June 2007, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by MDeC’s Undergraduate Skills Programme (USP).
27. Participant, Synthesizable Verilog HDL and Custom Design Front-End with Mentor Graphics, 7th – 10th May 2007, Universiti Teknologi Mara Malaysia, organized by CEDEC.
28. Participant, IC Design using Verilog HDL with Mentor Graphics, 23th – 26th Jan 2007, Universiti Sains Malaysia, organized by CEDEC.
29. Instructor, Altera Quartus II EDA Design Software Workshop. 13th January 2006, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by IEEE UTM Student Branch and Altera Corporation.
30. Instructor, VHDL Design of Digital System with Altera Quartus II and Prototyping SoC-based Designs with Altera Nios development System Workshop Series, 21st – 29th July 2006, faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by IEEE UTM Student Branch and Altera Corporation.
31. Instructor. Altera SOPC Builder and Nios System Workshop,7th April 2006, faculty of Electrical Engineering, Universiti Teknologi Malaysia, organized by IEEE UTM Student Branch and Altera Corporation.
